PTP end-to-end transparent clock for time of day/phase recovery is supported on the following:
the fixed platforms listed in Table: IEEE 1588v2 PTP Support per Fixed Platform
2-port 10GigE (Ethernet) module
Transparent clock functionality is supported for PTP packets over UDP/IP over Ethernet (with and without VLAN tags).
For high-accuracy 1588 PTP clock recovery, timestamping of incoming and outgoing messages should be done as close to ingress and egress as possible when the 7705 SAR is acting as a 1588 transparent clock. Edge timestamping is performed on all packets from all Ethernet ports, including SFP and RJ-45 ports on the faceplate of the chassis or a port on an installed module.
PTP recovered time accuracy depends on the delay of the forward path and the reverse path being symmetrical. It is possible to correct for known path delay asymmetry by using the ptp-asymmetry command to configure an asymmetry delay setting in nanoseconds per direction for each edge.
To enable transparent clock processing at the node level, configure a PTP clock with the transparent-e2e clock type (using the clock-type command). Deconfiguring such a PTP clock disables transparent clock processing.