The IEEE 1588v2 standard synchronizes the frequency and time from a timeTransmitter clock to one or more timeReceiver clocks over a packet stream. This packet-based synchronization can be over IP/UDP unicast or Ethernet multicast.
As part of the basic synchronization timing computation, event messages are defined for synchronization messaging between the PTP timeReceiver clock and PTP timeTransmitter clock. A one-step or two-step synchronization operation can be used; the two-step operation requires a follow-up message after each synchronization message.
The 7210 SAS-D ETR supports only two-step timeTransmitter port operation. All platforms can operate timeReceiver ports that receive from a one-step or two-step timeTransmitter port.
During startup, the PTP timeReceiver clock receives synchronization messages from the PTP timeTransmitter clock before a network delay calculation is made. Before any delay calculation, the delay is assumed to be zero. A drift compensation is activated after a number of synchronization message intervals occur. The expected interval between the reception of synchronization messages is user-configurable.
The following figure shows the basic synchronization timing computation between the PTP timeReceiver clock and PTP best timeTransmitter, as well as the offset of the timeReceiver clock referenced to the best timeTransmitter signal during startup.
When the IEEE 1588v2 standard is used for distribution of a frequency reference, the timeReceiver calculates a message delay from the timeTransmitter to the timeReceiver based on the timestamps exchanged. A sequence of these calculated delays contains information about the relative frequencies of the timeTransmitter clock and timeReceiver clock, but also includes a noise component related to the PDV experienced across the network. The timeReceiver must filter the PDV effects to extract the relative frequency data and then adjust the timeReceiver frequency to align with the timeTransmitter frequency.
When the IEEE 1588v2 standard is used for distribution of time, the 7210 SAS calculates the offset between the 7210 SAS time base and the external timeTransmitter clock time base based on the four timestamps exchanged. The 7210 SAS determines the offset adjustment, and between these adjustments, it maintains the progression of time using the frequency from the central clock of the node. This allows time to be maintained using a Synchronous Ethernet input source even if the IEEE 1588v2 communications fail. When using IEEE 1588v2 for time distribution, the central clock should, at a minimum, have the PTP input reference enabled.
The following figure shows the logical model for using PTP/1588 for network synchronization.
